As the semiconductor industry has continued to progress toward increasingly smaller devices, complementary metal-oxide-semiconductor (CMOS) circuits have become increasingly more highly integrated. Consequently, the individual devices which are combined to form CMOS circuits have become increasingly smaller. In some instances, the scaling down of these devices has created a need for new technologies, as existing technologies have run into fundamental limitations that prevent the devices from being scaled down any further.
For example, in conventional metal-oxide-silicon field effect transistor (“MOSFET”) devices in which a gate controls a channel and the channel provides a path between a source region and a drain region of the device, the smaller dimensions of the channel may cause the source and drain regions to be too close to one another. As a result of the shortened distance, leakage current may flow between the source and drain regions. Additionally, the ability to control the gate may be decreased.
To address these issues, double gate field effect transistors and, in particular, fin-type field effect transistors (FinFETs), have been developed. FinFETs are capable of relatively high transconductance and improved short-channel effects, and include two gate conductors that surround a non-planarized channel. To produce the desired FinFET structure, a substrate is subjected to a complex manufacturing process that typically includes deposition, etching, and planarization steps which provide suitable conductor, semiconductor, and insulating layers and which form the appropriate components of the FinFET structures from these layers.
Although FinFETs have a number of desirable properties, they can also be relatively costly and time-consuming to produce. As a result, manufacturers have begun exploring the use of other types of double gate devices, such as, for example, planar double gate devices. Planar double gate devices typically include a top gate, a bottom gate, and a channel interposed therebetween.